The invention relates to semiconductor packages, to intermediate products, such as a panel, and to methods of producing the panel and the semiconductor packages.
The reduction of the size and reduction of the cost of semiconductor packages is a long-standing desire in the development of semiconductor packages. It is desired to decrease both the footprint of the package, i.e. the lateral dimensions of the package, so that the space required to mount the package on the board is reduced, and the thickness of the package.
The cost of the semiconductor package can be reduced by reducing the materials costs by, for example, reducing the size of the package or through the choice of the materials. However, a greater cost saving can usually be achieved by simplifying and streamlining the production and assembly processes.
One approach to solving these problems is to provide a leadless semiconductor package, as is known, for example, from US 2004/0017668. In this method, a package substrate is prepared by forming a structured metal foil layer on a temporary carrier using photolithographic techniques. After the semiconductor chip is mounted to and electrically connected to the structured metal layer, the semiconductor chip, bond wires and the structured metal layer are embedded in molding compound to form a molded package. The temporary carrier is then removed to form a leadless semiconductor package in which the lower surfaces of the structured metal layer are exposed from the mold compound and provide the external contact areas of the package.
The prior art packages have the disadvantage that they are complicated and, therefore, costly to produce as a structured metal layer is produced to provide a substrate for the package.
For these and other reasons there is a need for the present invention.